1. Field of the Invention
The present invention in general relates to a semiconductor technology, More specifically, the present invention relates to electrostatic discharge clamp circuits for providing an electrostatic discharge current path before electrostatic discharge current flow through a core device to keep the core device from being destroyed.
2. Description of the Related Art
Different voltage levels are applied to I/O and core devices, and the voltage level of the I/O devices is usually higher than that of the core devices. Usually, MOS components of the I/O devices have thicker oxide thickness, deeper source/drain junction. Therefore, the I/O devices are more immune to ESD zap. This is the reason why use the I/O devices as an ESD clamp circuit. In deep submicron technology, core devices are drawn with minimum dimension and spacing that they have lower breakdown voltage and are easier damaged by ESD zap. However the conventional ESD protection circuits implemented by I/O devices require higher trigger voltage, and can not effectively bypass the electrostatic discharge currents before ESD damage the core circuits.
FIG. 1 shows a conventional ESD protection scheme and an ESD current path for a whole chip. As shown in FIG. 1, clamp circuit 2 is connected between input-output voltage source VDDIO and low voltage source VSS. Pull up clamp circuit 4 is connected between pad 1 and input-output voltage source VDDIO. Clamp circuit 6 is connected between pad 1 and low voltage source VSS. Clamp circuit 8 is connected between input-output voltage source VDDIO and core voltage source VDDCORE. Core circuit 30 is connected between core voltage source VDDCORE and low voltage source VSS. And conventional clamp circuit 20 is connected between core voltage source VDDCORE and low voltage source VSS. Clamp circuit 20, which is used as a protection circuit to prevent ESD current flow through core circuit 30, is fabricated by a process that fabricates I/O device.
As shown in FIG. 1, ESD current path 100 illustrates the prior art ESD current path in an integrated circuit. Because clamp circuit 20 connected between core voltage source VDDCORE and low voltage source VSS is fabricated by a process which fabricates I/O device, its trigger voltage is high. And it can not turn on conducting ESD current before core circuit 30 is destroyed that ESD current punch through core circuit 30 and conduct to low voltage source VSS. When a positive ESD voltage is applied to pad 1 and input-output voltage source VDDIO and core voltage source VDDCORE are both floating, the ESD current is conducted into input-output voltage source VDDIO through pull up clamp circuit 4, which is connected between pad 1 and input-output voltage source VDDIO. And then the ESD current is conducted into core voltage source VDDCORE through clamp circuit 8, which is connected between input-output voltage source VDDIO and core voltage source VDDCORE. Because core circuit 30 has device dimensions and layout spacings smaller than that of clamp circuit 20, it is vulnerable to ESD zap before clamp circuit 20 turn on conducting ESD current. So the ESD current path 100 conducts into low voltage source VSS through core circuit 30, and then conducts into another pad through low voltage source VSS.